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HM628100I Series
Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit)
ADE-203-1302B (Z) Rev. 1.0 Sep. 25, 2002
Description
The Hitachi HM628100I Series is 8-Mbit static RAM organized 1,048,576-word x 8-bit. HM628100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin TSOP II for high density surface mounting.
Features
* * * Single 5.0 V supply: 5.0 V 10 % Fast access time: 55 ns (max) Power dissipation: Active: 10 mW/MHz (typ) Standby: 7.5 W (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: -40 to +85C
* * * * *
HM628100I Series
Ordering Information
Type No. HM628100LTTI-5SL Access time 55 ns Package 400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE)
2
HM628100I Series
Pin Arrangement
44-pin TSOP A4 A3 A2 A1 A0 CS1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CS2 A8 NC NC I/O7 I/O6 VSS VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14
Pin Description (TSOP)
Pin name A0 to A19 I/O0 to I/O7 CS1 CS2 WE OE VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Power supply Ground No connection
3
HM628100I Series
Block Diagram (TSOP)
LSB V CC V SS
* * * * *
A5 A6 A7 A4 A3 A9 A10 A11 A12 A13 MSB A14
Row decoder
Memory matrix 2,048 x 4,096
I/O0 Input data control I/O7
* *
Column I/O Column decoder
* *
LSB
MSB A16 A17A18 A19 A0 A1 A2 A15A8
* *
CS2 CS1 Control logic WE OE
4
HM628100I Series
Operation Table
CS1 H x L L L CS2 x L H H H WE x x H L H OE x x L x H I/O0 to I/O7 High-Z High-Z Dout Din High-Z Operation Standby Standby Read Write Output disable
Note: H: V IH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to + 7.0 -0.5* to V CC + 0.3* 1.0 -55 to +125 -40 to +85
1 2
Unit V V W C C
Notes: 1. VT min: -3.0 V for pulse half-width 30 ns. 2. Maximum voltage is +7.0 V.
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 4.5 0 2.2 -0.3 -40 Typ 5.0 0 -- -- -- Max 5.5 0 VCC + 0.3 0.8 85 Unit V V V V C 1 Note
1. VIL min: -3.0 V for pulse half-width 30 ns.
5
HM628100I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | -- -- Typ* 1 Max -- -- 1 1 Unit A A Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, or VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/VIL, I I/O = 0 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS1 0.2 V, CS2 V CC - 0.2 V VIH V CC - 0.2 V, VIL 0.2 V CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1 V CC - 0.2 V, CS2 V CC - 0.2 V I OH = -1 mA I OL = 2.1 mA
Operating current Average operating current
I CC I CC1
-- --
-- 14
20 25
mA mA
I CC2
--
2
4
mA
Standby current Standby current
I SB I SB1
-- --
0.1 0.8
0.3 10
mA A
Output high voltage Output low voltage Note:
VOH VOL
2.4 --
-- --
-- 0.4
V V
1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed.
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
6
HM628100I Series
AC Characteristics (Ta = -40 to +85C, VCC = 5.0 V 10 %, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (50 pF) (Including scope and jig)
Read Cycle
HM628100I -5 Parameter Read cycle time Address access time Chip select access time Symbol t RC t AA t ACS1 t ACS2 Output enable to output valid Output hold from address change Chip select to output in low-Z t OE t OH t CLZ1 t CLZ2 Output enable to output in low-Z Chip deselect to output in high-Z t OLZ t CHZ1 t CHZ2 Output disable to output in high-Z t OHZ Min 55 -- -- -- -- 10 10 10 5 0 0 0 Max -- 55 55 55 35 -- -- -- -- 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
7
HM628100I Series
Write Cycle
HM628100I -5 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ Min 55 50 50 40 0 0 25 0 5 0 0 Max -- -- -- -- -- -- -- -- -- 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 5 4 6 7 Notes
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle.
8
HM628100I Series
Timing Waveform
Read Cycle
t RC Address tAA tACS1 CS1 tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address
CS2
tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tOHZ*1, 2, 3 tOE
OE tOLZ*2, 3 Dout High impedance Valid data tOH
9
HM628100I Series
Write Cycle (1) (WE Clock)
tWC Address Valid address tWR*7
tCW*5 CS1 tCW*5 CS2
tAW tWP*4
WE
tAS*6 tDW tDH
Din tWHZ*1, 2
Valid data tOW*2 High impedance
Dout
10
HM628100I Series
Write Cycle (2) (CS Clock, OE = VIH)
tWC Address Valid address tAW tAS*6 CS1 tCW*5 CS2 tWP*4 WE tDW Din Valid data tDH tCW*5 tWR*7
High impedance Dout
11
HM628100I Series
Low VCC Data Retention Characteristics (Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 2 -- Max -- Unit V Test conditions*1 Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V CS1 V CC - 0.2 V VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V See retention waveform
Data retention current
I CCDR
--
0.8
10
A
Chip deselect to data retention time Operation recovery time
t CDR tR
0 t RC* 3
-- --
-- --
ns ns
Notes: 1. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 V CC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 2. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 3. t RC = read cycle time.
12
HM628100I Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
Data retention mode tR
t CDR VCC 4.5 V
2.2 V VDR CS1 0V CS1 VCC - 0.2 V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR VCC 4.5 V CS2 VDR 0.8 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
13
HM628100I Series
Package Dimensions
HM628100LTTI Series (TTP-44DE)
As of January, 2002
18.41 18.81 Max 44 23
Unit: mm
1 *0.27 0.07 0.25 0.05
0.80 0.13 M
22 0.80
10.16
1.005 Max *0.145 0.05 0.125 0.04
11.76 0.20 0.50 0.10 0.68 0 - 5 0.13 0.05
1.20 Max
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC JEITA Mass (reference value)
TTP-44DE -- -- 0.43 g
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